1. Field of the Invention
The present invention relates to a stackable semiconductor chip package, methods of making the chip package and a stacked semiconductor chip module.
2. Background of the Related Art
Generally, a 3-dimensional chip stacking technique is used for implementing a highly-integrated semiconductor chip package having a high capacity and small size. Examples of these techniques are disclosed in U.S. Pat. No. 5,104,820 and U.S. Pat. No. 5,279,991.
FIG. 1 shows an uncut wafer having a chip portion 11. As shown in FIG 1, in the 3-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,104,820, a plurality of pads 12 aligned on the upper surface of each chip portion 11 are extended, using conductive patterns 13, to lateral portions of the chip 11. This is done while the wafer is still uncut. The wafer is then cut into a plurality of parts as semiconductor chips, each having realigned pads 14. The cut and separated semiconductor chips are stacked to form a semiconductor chip module, and the lateral portions of each semiconductor chip are insulated. To accomplish the lateral surface insulation process, the semiconductor chips having the realigned pads are first stacked in a multiple-tier structure. The lateral portions of each semiconductor chip are etched so that the end portions (realigned pad portions) 14 of the conductive patterns 13 are not damaged, and a polymer insulation member is filled into the etched portions. This insulates the lateral portions of each semiconductor chip.
The 3-dimensional chip stacking technique disclosed in the U.S. Pat. No. 5,104,820 has several disadvantages. First, since the lateral portion insulating process is performed after a wafer has been cut into chips, and the chips have been stacked to form a chip module, wafer conventional processing techniques cannot be used to accomplish the lateral insulation process. Second, in order to form the realigned pads 14, areas of the wafer that would normally be used to form neighboring chips are used, and the yield of the semiconductor chip fabrication is decreased.
In the 3-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,279,991, chip modules, each consisting of a plurality of semiconductor chips having realigned pads, are stacked to form a large unit of stacked modules. The lateral portions of each semiconductor chip are then insulated. The large unit of the stacked modules may then be separated into smalls units of modules, if necessary, based on the purpose of its use.
However, in this technique, since some processes are performed on the stacked semiconductor chips in a manner similar to that of U.S. Pat. No. 5,104,820, known wafer processing techniques are not used to form the lateral insulation portions. This makes the fabrication processes complicated, and some additional apparatus is needed.
The above references are incorporated by reference herein where appropriate for teachings of additional or alternative details, features and/or technical background.